Methods of Forming Semiconductor Constructions

ABSTRACT

The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.

TECHNICAL FIELD

The invention pertains to methods of forming semiconductorconstructions, and in particular aspects pertains to methods of formingcapacitors associated with semiconductor constructions.

BACKGROUND OF THE INVENTION

Capacitors continue to have increasing aspect ratios in highergeneration integrated circuitry fabrication. For example, dynamic randomaccess memory (DRAM) capacitors now have elevations of from 2 to 3microns, and widths of about 0.1 micron. Further, it is a continuinggoal to increase the density of semiconductor devices, with acorresponding goal to reduce the footprint associated with individualdevices. As the packing density of capacitors becomes increasinglygreater, the available surface area for capacitance decreases.

A common type of capacitor is a so-called container device, which istypically in cylindrical form. One of the electrodes of such device isshaped as a container, and subsequently dielectric material and anothercapacitor electrode are formed within the container. Typically, only theinterior surfaces of the containers are being utilized for capacitancesurface area. It would be desirable to utilize exterior surfaces of thecontainers for capacitance as well. Unfortunately, exposure of both theinterior and exterior surfaces of a container having a high aspect ratiocan render the container structurally weak, and subject to toppling orbreaking from an underlying base. It would therefore be desirable todevelop methods which enable exterior surfaces of high aspect ratiocontainers to be utilized as capacitive surfaces while avoiding topplingor other loss of structural integrity of the high aspect ratiocontainers.

Exemplary methodology being developed to avoiding toppling of highaspect ratio containers is so-called lattice methodology. In suchmethodology, a lattice is provided to hold container-shaped electrodesfrom toppling, while leaving outer surfaces of the container-shapedelectrodes exposed for utilization as capacitive surfaces of capacitors.During lattice methodology, container-shaped electrodes are formed inopenings in a supporting material (such as, for example,borophosphosilicate glass (BPSG)), and then the supporting material isremoved with an isotropic etch.

The supporting material is commonly over a memory array region and overa peripheral region adjacent the memory array region, and is only to beremoved from the memory array region during the etch. A moat willtypically be provided between the memory array region and the peripheralregion, and one or more protective layers will be within the moat andover the peripheral region to protect the supporting material of theperipheral region during the isotropic etching of such material from thememory array region. As will be discussed in more detail later in thisdisclosure, it can be desired to provide sacrificial silicon-containingmaterial within the container-shaped electrodes, and within the moatbetween the memory array region and the peripheral region, to protectvarious materials during the isotropic etch of the supporting material.Difficulties can occur during removal of the sacrificialsilicon-containing material, and in some aspects the invention describedherein addresses such difficulties.

SUMMARY OF THE INVENTION

in one aspect, the invention includes a method of forming asemiconductor construction. Upwardly-opening titanium-containingcontainer structures are formed within a first material and over asemiconductor substrate. Silicon is formed within the upwardly-openingcontainer structures. After the silicon is formed, at least some of thefirst material is removed to exposed outer services of theupwardly-opening container structures. The silicon is then removed withan etching solution having a phosphorus-and-oxygen-containing compoundtherein.

In one aspect, the invention includes a method of forming a plurality ofcapacitors. A first material is formed over a semiconductor substrate,and openings are formed to extend into the first material.Titanium-containing material is formed within the openings to narrow theopenings. Silicon is formed within the narrowed openings. The silicon isremoved with an etch utilizing an etching solution containing at leastone nitrogen-containing etchant and at least onephosphorus-and-oxygen-containing compound. The titanium-containingmaterial is then incorporated into a plurality of capacitors.

In one aspect, the invention includes another method of forming aplurality of capacitors. An assembly is provided which comprises asemiconductor substrate supporting a plurality of electrical nodes, afirst material over the semiconductor substrate, and an electricallyinsulative retaining material over the first material. Openings areformed to extend through the retaining material and the first materialto the electrical nodes. Capacitor electrode material is formed in theopenings to narrow the openings, and silicon is formed within thenarrowed openings. While the silicon is within the narrowed openings, atleast some of the first material is etched with an isotropic etchselective for the first material relative to the retaining material. Thesilicon is then removed with a silicon etch. The silicon etch formswhiskers of the capacitor electrode material. The whiskers are removedwith an etch, and then the conductive capacitor electrode materialremaining within the openings is incorporated into a plurality ofcapacitors.

In one aspect, the invention includes yet another method of forming aplurality of capacitors. A construction is provided which comprises amemory array region, a region other than the memory array region, and alocation between the memory array region and said other region. A firstmaterial is formed to extend over the memory region, over said otherregion, and over the location between the memory array region and saidother region. A second material is formed over at least a portion of thefirst material that is over the memory array region and over an entiretyof the first material that is over said other region. Openings areformed to extend into the first material over the memory region and atrench is formed within the first material over the location between thememory region and said other region. A first conductive material isformed in the openings and within the trench. The first conductivematerial within the openings forms container structures having outersidewalls along the first material. Silicon is formed within the trenchand within the openings. After the silicon is formed, at least some ofthe first material is removed to expose at least portions of the outersidewalls of the container structures. The silicon is removed with anetching composition having at least one phosphorus-and-oxygen-containingcompound dispersed therein. A capacitor dielectric material is formedalong the exposed portions of the outer sidewalls and within thecontainer structures. A second conductive material is formed over thecapacitor dielectric material.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic, cross-sectional view of a semiconductor waferfragment at a preliminary processing stage of an exemplary aspect of thepresent invention.

FIG. 2 is a fragmentary top view of a semiconductor wafer fragmentcomprising the cross-section of FIG. 1 along the line 1-1.

FIG. 3 is a diagrammatic, cross-sectional view of the FIG. 1 waferfragment shown at a processing step subsequent to that of FIG. 1.

FIG. 4 is a fragmentary top view of a semiconductor constructioncomprising the fragment of FIG. 3 along the line 3-3.

FIG. 5 is a diagrammatic, cross-sectional view of the semiconductorwafer fragment of FIG. 1 at a processing stage subsequent to that ofFIG. 3.

FIG. 6 is a diagrammatic top view of a semiconductor constructioncomprising the fragment of FIG. 5 along the line 5-5.

FIG. 7 is a view of the cross-section of FIG. 1 shown at a processingstage subsequent to that of FIG. 5.

FIG. 8 is a diagrammatic top view of a semiconductor wafer fragmentcomprising the cross-section of FIG. 7 along the line 7-7.

FIG. 9 is a diagrammatic, cross-sectional view along the line 9-9 of theFIG. 8 fragment, and illustrates a slightly different aspect of theinvention than FIGS. 7 and 8.

FIG. 10 is a view of the cross-section of FIG. 1 shown at a processingstage subsequent to that of FIG. 7.

FIG. 11 is a diagrammatic top view of a semiconductor constructioncomprising the cross-section of FIG. 10 along the line 10-10.

FIG. 12 is a diagrammatic cross-section along the line 12-12 of FIG. 11.

FIG. 13 is a view of the cross-section of FIG. 1 shown at a processingstage subsequent to that of FIG. 10.

FIG. 14 is a diagrammatic top view of a fragment of a semiconductorconstruction comprising the cross-section of FIG. 13 along the line13-13.

FIG. 15 is a diagrammatic, cross-sectional view along the line 15-15 ofFIG. 14.

FIG. 16 is a view of the FIG. 1 cross-section shown at a processingstage subsequent to that of FIG. 13.

FIG. 17 is a diagrammatic top view of a semiconductor wafer fragmentcomprising the cross-section of FIG. 16 along the line 16-16.

FIG. 18 is a diagrammatic, cross-sectional view along the line 18-18 ofFIG. 17.

FIG. 19 is a view of the FIG. 1 cross-section shown at a processingstage subsequent to that of FIG. 10, illustrating an aspect alternativeto that of FIG. 16 and showing a problem that can occur if theprocessing of FIGS. 13-15 is omitted.

FIG. 20 is a view of the FIG. 1 cross-section shown at a processingstage subsequent to that of FIG. 16 illustrating a problem that cansometimes occur.

FIG. 21 is a view of the FIG. 1 cross-section shown at a processingstage subsequent to that of FIG. 16.

FIG. 22 is a diagrammatic top view of a semiconductor wafer fragmentcomprising the cross-section of FIG. 21 along the line 21-21.

FIG. 23 is a diagrammatic, cross-sectional view along the line 23-23 ofFIG. 21.

FIG. 24 is a diagrammatic top view of a fragment of a semiconductorconstruction illustrating an exemplary liner formed in accordance withan aspect of the present invention.

FIG. 25 is a diagrammatic top view of a fragment of a semiconductorconstruction illustrating another exemplary liner formed in accordancewith an aspect of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

The invention includes methodology for forming container capacitors. Intypical processing, a semiconductor wafer will have a memory arrayregion where capacitors are to be formed. It can be desired to etchsacrificial silicon-containing material from the memory array region,while avoiding formation of conductive whiskers from storage nodematerial exposed to the etch. Methodology of the present invention caninclude dispersal of phosphoric acid in the etching solution utilized toremove the silicon to alleviate the formation of the conductivewhiskers. The invention can additionally, or alternatively, includemethodology for removing any whiskers that have formed.

Various aspects of the invention are described below with reference toFIGS. 1-25.

Referring to FIG. 1, a semiconductor wafer fragment 10 is shown at apreliminary processing stage of an exemplary aspect of the presentinvention. Fragment 10 comprises a substrate 12. Substrate 12 cancomprise, consist essentially of, or consist of, for example,monocrystalline silicon lightly-doped with background p-type dopant. Toaid in interpretation of the claims that follow, the terms“semiconductive substrate” and “semiconductor substrate” are defined tomean any construction comprising semiconductive material, including, butnot limited to, bulk semiconductive materials such as a semiconductivewafer (either alone or in assemblies comprising other materialsthereon), and semiconductive material layers (either alone or inassemblies comprising other materials). The term “substrate” refers toany supporting structure, including, but not limited to, thesemiconductive substrates described above.

Substrate 12 is divided into three defined regions 14, 16 and 18. Region14 corresponds to a memory array region. Region 18 corresponds to aregion other than the memory array region, and can correspond to, forexample, a so-called peripheral region. The region is referred to as aperipheral region because it is peripheral to the memory array region.Typically, logic circuitry and other circuitry associated with thecontrol of data flow to and from memory devices associated with memoryarray region 14 would be associated with peripheral region 18. Region 16corresponds to a location between the memory array region 14 and theperipheral circuitry associated with region 18. Dashed lines areprovided through construction 10 to demarcate the various definedregions 14, 16 and 18 extending within the structure. Various circuitdevices (not shown) could be associated with region 18 at the processingstage of FIG. 1.

A plurality of electrically conductive node locations 20, 22, 24 and 26are shown within memory array region 14 of substrate 12. Node locations20, 22, 24 and 26 can correspond to, for example, conductively-dopeddiffusion regions within a semiconductive material of substrate 12,and/or to conductive pedestals associated with substrate 12. Althoughthe node locations are shown to be electrically conductive at theprocessing stage of FIG. 1, it is to be understood that the electricallyconductive materials of the node locations could alternatively beprovided at a processing stage subsequent to that of FIG. 1. Nodelocations 20, 22, 24 and 26 can ultimately be electrically connectedwith transistor constructions (not shown in FIG. 1) and can correspondto source/drain regions of the transistor constructions, or can beohmically connected to source/drain regions of the transistorconstructions. Transistor gates and other components of the transistorconstructions can be present within memory array region 14 at theprocessing stage of FIG. 1, or can be formed in subsequent processing.

A mass 28 is formed over substrate 12. Mass 28 can comprise a singlehomogeneous layer (as shown), or can comprise multiple layers ofdiffering composition and/or physical properties. Mass 28 can comprise,consist essentially of, or consist of one or more electricallyinsulative materials. In particular aspects, mass 28 will comprise,consist essentially of, or consist of one or more of borophosphosilicateglass (BPSG), spin-on-glass (SOG), silicon dioxide, phosphosilicateglass (PSG), borosilicate glass (BSG), undoped glass, and siliconnitride. In some aspects, mass 28 will comprise, consist essentially of,or consist of silicon and oxygen. Mass 28 can have a thickness oversubstrate 12 of, for example, from about 5,000 Å to about 50,000 Å, andtypically will have a thickness of about 20,000 Å.

A retaining structure (also referred to as a lattice structure) 30 isformed over mass 28. Retaining structure 30 can comprise a singlehomogeneous composition, or can comprise two or more layers of differingcomposition. In subsequent processing (described below) at least some ofmass 28 is selectively etched relative to at least some of retainingmaterial 30. Accordingly, retaining material 30 preferably comprises acomposition to which at least some of mass 28 can be selectively etched.In particular aspects, mass 28 can be considered to comprise a firstmaterial, and structure 30 can be considered to comprise a secondmaterial to which the first material is ultimately selectively etched.In some aspects, retaining structure 30 will comprise, consistessentially of, or consist of silicon and nitrogen. In an exemplaryaspect, mass 28 will comprise, consist essentially of, or consist ofborophosphosilicate glass and retaining structure 30 will comprise,consist essentially of, or consist of silicon nitride. If retainingstructure 30 consists essentially of, or consists of silicon nitride,the structure can have a thickness of from about 50 Å to about 3,000 Å,and typically will have a thickness of about 700 Å.

FIG. 2 shows a top view of a semiconductor wafer fragment comprising theFIG. 1 cross-section, and shows retaining structure 30 extendingentirely across the upper surface of the semiconductor construction.

Referring next to FIGS. 3 and 4, openings 32, 34, 36, 38, 40, 42, 44,46, 48, 50, 52 and 54 are formed through retaining structure 30 and mass28, and to the node locations associated with an upper surface ofsubstrate 12, (with the node locations 20, 22, 24 and 26 being shown inFIG. 3). The openings can have a very high aspect ratio, and ultimatelyare utilized for forming capacitor containers (as discussed below). Inparticular aspects, the openings can have an elevation of from about 2to about 3 microns, and a maximum width of about 0.1 micron. Theopenings are shown to have circular outer peripheries (as illustrated bythe top view of FIG. 4), but it is to be understood that the openingscan have other shapes. The openings 32, 34, 36, 38, 40, 42, 44, 46, 48,50, 52, and 54 are ultimately utilized to form containers of capacitors,as discussed in more detail below.

The openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, and 54 areformed over memory array region 14 of construction 10, and while theopenings are formed a trench (or moat) 56 is formed within location 16of construction 10.

The formation of the container openings within memory array region 14,and the trench within location 16, would typically be accomplished byfirst forming a photoresist mask (not shown) with photolithographicprocessing, and subsequently transferring a pattern from the patternedmask to underlying materials 28 and 30, followed by removal of thepatterned photoresist mask. The photolithographic requirementsassociated with formation of the patterned mask can be relativelystringent, and accordingly an antireflective layer (not shown) can beincorporated into structure 30, formed beneath structure 30, or formedover structure 30 in various aspects of the present invention. Theantireflective coating can comprise, for example, either a hard film(for example, dielectric antireflective coating, (DARC)), or a spin-onfilm (for example, bottom antireflective coating, (BARC)).

Openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54 are formed inan array within memory region 14. Such array comprises rows and columns.The rows can be considered to extend horizontally in the view of FIG. 4,and the columns can be considered to extend vertically in the view ofFIG. 4.

Although openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54 aredescribed as extending through material 28 to underlying conductivenodes (such as nodes 20, 22, 24, and 26) it is to be understood that oneor more other layers (not shown) can be provided between the nodes andmaterial 28, and that the openings can stop on the other layers. Forinstance, an etch stop layer (not shown) can be provided betweenmaterial 28 and nodes 20, 22, 24, and 26 so that the openings stop onthe etch stop layer. The etch stop layer can protect underlyingmaterials (such as the surface of substrate 12 and/or electrical devices(not shown)) supported by the surface during a subsequent isotropic etchof material 28 (discussed below). The openings can be extended throughthe etch stop and to nodes 20, 22, 24, and 26 with a second etch afterthe etch through material 28. The etch stop can comprise any suitablematerial to which material 28 can be selectively etched, and can, forexample, comprise, consist essentially of or consist of silicon nitride.

Referring next to FIGS. 5 and 6, an electrically conductive material 60is formed within openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and54, as well as within trench 56. Conductive material 60 can be ahomogeneous composition, or can comprise multiple layers. Accordingly,material 60 can comprise, consist essentially of, or consist of one ormore electrically conductive compositions. The electrically conductivecompositions within material 60 can be any suitable compositions,including, for example, conductively-doped silicon, metal, and metalcompounds. In particular aspects, material 60 be a titanium-containingmaterial, and in such aspects material 60 can, for example, comprise atitanium nitride layer over a titanium layer. The titanium nitride layercan comprise, consist essentially of, or consist of titanium nitride,and the titanium layer can comprise, consist essentially of, or consistof titanium (in elemental form, and/or in a multi-element compound, suchas, for example, titanium silicide).

Portions of material 60 within the openings in memory array region 14can be considered to form upwardly-opening container structures withinthe openings. For instance, FIG. 5 shows the portions of material 60within openings 40, 42, 44 and 46 corresponding to containerconstructions 62, 64, 66 and 68. The container constructions can beconsidered to comprise inner surfaces 70 within the openings and outersurfaces 72 laterally opposed to the inner surfaces. The outer surfaces72 extend along mass 28 and retaining structure 30.

Conductive material 60 is ultimately incorporated into capacitorelectrodes, and in particular aspects can be incorporated into capacitorstorage nodes. Accordingly, material 60 can be referred to as capacitorelectrode material, and in particular aspects can be referred to as astorage node material.

Referring next to FIGS. 7-9, conductive material 60 is removed from overan upper surface of structure 30 to electrically isolate conductivestructures within openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52and 54 (such as, for example, the container structures 62, 64, 66 and 68of FIG. 7) from one another. An exemplary method for removing conductivematerial 60 from over upper surface 30 is chemical-mechanical polishing.

After removal of material 60 from over the upper surface of structure30, a patterned mask 80 is formed over memory array region 14,peripheral region 18, and the location 16 between regions 14 and 18.Mask 80 entirely covers regions 16 and 18, but is patterned over region14 to form rows 82 connecting pairs of capacitor rows. Portions ofmaterial 60 in openings 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and54 are shown in phantom view in FIG. 8 to indicate that such portionsare covered by masking material 80. An exemplary material of mask 80 isphotoresist, and such can be formed into the shown pattern utilizingphotolithographic processing. The illustrated shape of patterned mask 80is but one of many possible patterns that can be utilized. The shownshape of patterned mask 80 has strips extending horizontally relative tothe view of FIG. 8. In other exemplary shapes (not shown) patternedstrips of material 80 can extend to entirely cover particularcontainers, to extend diagonally relative to the view of FIG. 8 and/orto extend vertically relative to the view of FIG. 8.

The conductive material 60 within trench 56 is shown in phantom view inFIG. 8 to indicate that such material is covered by masking material 80.

FIG. 9 shows containers 84 and 86 associated with openings 34 and 50, inaddition to the container 64 associated with opening 42. Containers 84and 86 extend to node locations 85 and 87, which can comprise similarconstructions to those described above relative to node location 22.Container constructions 84 and 86 comprise the interior peripheries 70and outer peripheries 72 described previously with reference tocontainers 62, 64, 66 and 68 of FIG. 5. In the shown aspect of theinvention, masking material 80 extends into openings 34, 42 and 50.Specifically, the masking material extends along the interior lateralsurfaces 70 of each of the openings, and in the shown aspect extendsentirely along at least one of the interior lateral surfaces 70 of eachof the openings. In typical processing, a sacrificial material (notshown) would be provided in openings 32, 34, 36, 38, 40, 42, 44, 46, 48,50, 52 and 54 during the above-described chemical-mechanical polishingof material 60. The sacrificial material can be removed from within theopenings at any suitable processing stage, which may be a stage beforeprovision of masking material 80, or a stage after provision of maskingmaterial 80. If the sacrificial material remains in the openings duringprovision of masking material 80, the sacrificial material may precludematerial 80 from entering the openings. In such aspects, material 80 maynot be along the interior surfaces of the openings, but instead would beover the openings. In some aspects it can be desired to leave thesacrificial material within the openings during provision of maskingmaterial 80 to alleviate thinning of material 80 that might otherwiseoccur, and in other aspects it can be desired to remove the sacrificialmaterial prior to formation of masking material 80. The illustration ofFIG. 9 is somewhat inconsistent with FIGS. 7 and 8 in that FIG. 9 showsmaterial 80 extending within the opening 42, and FIGS. 7 and 8 showopening 42 having a region within which material 80 does not extend.Thus, FIG. 9 illustrates a slightly different aspect of the inventionthan FIGS. 7 and 8.

Referring next to FIGS. 10-12, a pattern is transferred from maskingmaterial 80 (FIGS. 7-9), to retaining structure 30, and subsequently themasking material is removed.

Removal of structural material 30 exposes portions of the outer surfaces72 of the containers (for example, containers 62, 64, 66 and 68 of FIG.10) at uppermost regions of the containers. The material 30 of FIGS.10-12 has been patterned into a pattern from mask 80 (FIGS. 7-9), andaccordingly the material 30 remains continuous over peripheral region 18and intermediate region 16, and is patterned to comprise rows 102extending between pairs of capacitor container rows. For instance, thelower row 102 of FIG. 11 connects the horizontal row of capacitorcontainers containing the containers within openings 40, 42, 44 and 46with the row of capacitor containers that are within openings 48, 50, 52and 54. Retaining structure 30 physically contacts the material 60 ofthe capacitor containers within each row. In particular aspects, theretaining structure 30 can contact all of the container structuresassociated with an array over memory device region 14, and in otheraspects the retaining structure can contact only some of the capacitors.It can be preferred, however, that the retaining structure contact allof the devices in order to alleviate (and preferably prevent) topplingand other structural defects from occurring in the devices in subsequentprocessing (described below).

Referring to FIGS. 13-15, silicon-containing material 75 is formedwithin the upwardly-opening container structures 32, 34, 36, 38, 40, 42,44, 46, 48, 50, 52 and 54, as well is within the trench 56. In someaspects, the silicon-containing material can be consider to be formedwithin openings narrowed by the conductive material 60. Thesilicon-containing material 75 can be formed to any suitable thickness,and in some aspects will be formed to a thickness of about 130 Å.

The silicon-containing material can comprise, consist essentially of, orconsist of silicon, and can be either doped or undoped. In particularaspects, the silicon-containing material can comprise, consistessentially of, or consist of either amorphous or polycrystallinesilicon. In the shown aspect of the invention, the silicon-containingmaterial 75 is patterned to overlay retaining structure 30. Accordingly,the silicon-containing material 75 extends over peripheral region 18 andover the rows 102 extending between pairs of capacitor container rows.The silicon-containing material protects interfaces oftitanium-containing material 60 and retaining structure 30 of material28, as will be discussed in more detail below.

The silicon-containing material 75 can be formed in the shown patternwith a photolithographically-patterned photoresist mask which issubsequently removed. Although silicon-containing material 75 is shownto be formed and patterned after removal of masking material 80 (FIGS.7-9), it is to be understood that the invention can also include aspectsin which material 75 is formed prior to masking material 80 and ispatterned using masking material 80 as a mask.

Referring next to FIGS. 16-18, construction 10 is exposed to conditionswhich isotropically remove material 28 selectively relative to retainingstructure 30, and thereafter silicon-containing material 75 is removed.The etching can utilize, for example, a wet etch. For purposes ofinterpreting this disclosure and the claims that follow, an etch isconsidered to be selective for a first material relative to a secondmaterial if the etch removes the first material at a faster rate thanthe second material, including, but not limited to, conditions in whichthe second material is substantially not removed during the removal ofthe first material (i.e., conditions in which the rate of removal of thesecond material is essentially 0).

The removal of material 28 exposes outer surfaces 72 of the containerstructures (such as, for example, the container structures 62, 64, 66and 68 of FIG. 14). In the shown aspect of the invention, material 28 issubstantially entirely removed from over memory region 14, andaccordingly an entirety of outer surfaces 72 are exposed. It is to beunderstood that the invention encompasses other aspects in which only aportion of material 28 is removed by the isotropic etch, and accordinglywherein only portions of the outer surfaces 72 are exposed.

As discussed previously, a material resistant to the etch of material 28(i.e., an etch stop) can be provided under material 28 in aspects of theinvention which are not shown. If the etch stop material is present,such can protect features underlying the etch stop during the isotropicetch of material 28.

Retaining material 30 remains in physical contact with portions ofconductive material 60 of the containers formed from material 60, andaccordingly supports the containers. Retaining structure can thusalleviate, and even prevent, toppling or other structural defects fromoccurring within an array of container structures. Structural material30 can enable container structures having a high aspect ratio to beformed, and to have outer surfaces (72) exposed, while alleviating, andin particular aspects even preventing, toppling of the containers. Inthe aspect of the invention shown in FIG. 15, retaining material 30connects alternating pairs of rows of a container structure array.

The silicon-containing material 75 (FIGS. 13-15) within the trench 56,the conductive material 60 within the trench, and the materials 30 and75 over periphery 18 form a protective barrier (or shield) so that theisotropic etching of material 28 over memory region 14 does not extendinto the material 28 associated with peripheral region 18. Such canalleviate damage to circuitry (not shown) associated with peripheralregion 18 that could otherwise occur if an isotropic etch penetratedinto the material 28 associated with peripheral region 18. Theprotective material 60 within trench 56 forms a protective trough (ormoat) which protects material 28 of peripheral region 18 from theisotropic etch utilized in removing material 28 from over memory arrayregion 14. In the shown aspect of the invention, the moat isdouble-sided.

The silicon-containing material 75 (FIGS. 13-15) can protect interfacesbetween retaining structure 30 and titanium-containing material 60.Specifically, there will commonly be a less-then-perfect seal betweentitanium-containing material 60 and retaining structure 30. Suchless-then-perfect seal can be considered to constitute a defectiveregion where the titanium-containing material 60 interfaces withretaining structure 30. Etchant utilized during the isotropic etch ofmaterial 28 can penetrate through such defective region to undesirablyetch into the material 28 associated with peripheral region 18. Forinstance, FIG. 19 shows an exemplary structure resulting from anisotropic etch of material 28 without the protective silicon-containingmaterial 75 being in place to protect an interface between the retainingstructure 30 and the titanium-containing structure 60. Such has resultedin a cavity (or blowout region) 77 etching into the material 28 overperipheral region 18 during the isotropic etch of a material 28 over thememory array region 14. The shown cavity is relatively small, but it isto be understood that the cavity could be much larger so that devicesassociated with peripheral region 18 (such devices are not shown) becomedamaged.

The silicon-containing material 75 of FIGS. 13-15 can thus serve animportant purpose of protecting interfaces between retaining structure30 (which can be a nitride-containing structure) and titanium-containingmaterial 60. Unfortunately, utilization of silicon-containing material75 can introduce significant complications into the processing.Specifically, the silicon etch utilized to remove silicon-containingmaterial 75 can form whiskers (or bridges) of conductive materialextending between adjacent containers. Such is illustrated in FIG. 20where whiskers 79 of conductive material are shown to extend betweenadjacent containers and form conductive bridges extending between andconnecting containers 40, 42, 44 and 46 with one another, as well asconnecting container 46 with the conductive material 60 in moat 56. Isfound that the conductive whiskers tend to comprise titanium from thetitanium-containing material 60. Further, if titanium-containing show 60comprises both titanium and titanium nitride, it appears that thewhiskers will generally comprise primarily titanium, rather than alsocomprising titanium nitride.

The invention includes new etching procedures for removingsilicon-containing material 75 which can alleviate, and in some aspectsentirely eliminate, undesirable whisker formation; and also includesetches which can be utilized to remove whiskers to the extent that suchwhiskers form.

In one aspect of the invention, it is found that dispersion of at leastone phosphorus-and-oxygen-containing compound in the etchant utilized toremove silicon-containing material 75 can be effective to significantlyreduce titanium-containing whisker formation. Thephosphorus-and-oxygen-containing compound with typically be initiallyprovided in an etching solution as phosphoric acid, and thus the atleast one phosphorus-and-oxygen-containing compound can initiallycomprise, consist essentially of, or consist of phosphoric acid.

Generally, the etching solution utilized to remove thesilicon-containing material will comprise one or morenitrogen-containing etching compounds, such as, for example, ammoniumhydroxide and tetra-methyl ammonium hydroxide. The total concentrationof the one or more nitrogen-containing etching compounds can be fromabout 2 volume percent about to about 50 volume percent, and typicallywill be from about 5 volume percent to about 25 volume percent. Thephosphoric acid can be initially provided to a concentration of fromabout 0.1 volume percent to about 1 volume percent, and typically willbe provided to a concentration of from about 0.2 volume percent to about0.4 volume percent. Thus, a volume ratio of a total amount of the atleast one nitrogen-containing etching compound to the total amount ofthe at least one phosphorus-and-oxygen-containing compound can be fromabout 2:1 to about 500:1; and typically will be from a 20:1 to about500:1. An exemplary silicon etch of the present invention can utilizeabout 0.3 volume percent phosphoric acid and about 10 volume percentammonium hydroxide for the etching composition, thus will have a ratioof nitrogen-containing etching compound tophosphorus-and-oxygen-containing compound of about 300:1.

The amount of phosphoric acid provided within the etching solution is sosmall that the solution remains alkaline. Accordingly, even though theform of phosphorus-and-oxygen-containing compound initially providedwithin the etching solution may be phosphoric acid, it is generally aphosphate that is present in the etching solution under the conditionsthat the solution is used for etching the silicon-containing material75.

A silicon etch of the present invention can be conducted at atemperature of from about 20° C. to about 100° C., with an exemplarytemperature being from about 30° C. to about 60° C., and a typicaltemperature being about 55° C. It can be preferred that the etchingcomposition be stirred or otherwise agitated during the etching of thesilicon, as such can help to alleviate whisker formation.

It is found that the dispersion of the phosphorus-and-oxygen-containingcompound will slow an etch rate of material 75 relative to the ratewhich would occur if the phosphorus-and-oxygen-containing compound wereomitted. For instance an etch rate of silicon-containing material 75with a dilute ammonium hydroxide solution (i.e., a solution containingabout 3 volume percent NH₄OH) is about 550 Å/minute at a temperature of55° C., and such rate drops to about 300 Å/minute with the addition ofabout 3000 parts per million phosphoric acid. The reduction of etch ratemay seem disadvantageous, but the associated reduction of whiskerformation can be a significant advantage that more than offsets thedisadvantage of the reduced etch rate.

Phosphorus-and-oxygen-containing compounds, like phosphoric acid, can bemuch preferred over other potential additives for reducing whiskerformation. The phosphorus-and-oxygen-containing compounds do not attacktitanium nitride to the extent that other tested additives do. Forinstance, hydrogen peroxide, nitric acid, hydrochloric acid and sulfuricacid were tested as additives for preventing whisker formation, and allwere found to attack titanium nitride so aggressively that it wasdifficult to establish conditions that would alleviate whisker formationwhile still maintaining integrity of the material 60 within thecontainer structures.

If titanium-containing whiskers form, such can be removed with any etchsuitable for removing titanium, and in some applications it can bepreferred that such whiskers be removed with an etch which is selectivefor removal of titanium relative to titanium nitride. The reason that itcan be preferred to use an etch selective for titanium relative totitanium nitride is that such can reduce loss of conductive material 60from the capacitor storage nodes. Specifically, conductive material 60typically comprises a layer of titanium nitride over a layer oftitanium; and the whiskers formed during the etching ofsilicon-containing material 75 will typically primary comprise titaniumrather than titanium nitride. Thus, an etch selective for titaniumrelative to titanium nitride can remove the whiskers selectivelyrelative to at least a portion of the conductive material 60.

An etch utilized to remove the titanium-containing whiskers can, forexample, comprise one or more of hydrofluoric acid, ammonium fluoride,nitric acid and hydrogen peroxide. If the etch utilizes hydrofluoricacid, such can be present in the etching composition to a concentrationof from about 0.2 volume percent to about 1 volume percent; if the etchutilizes hydrogen peroxide, such can be present in the etchingcomposition to a concentration of from about 0.5 volume percent to about10 volume percent; and if the etch utilizes nitric acid, such can bepresent in the etching composition to a concentration of about 1 volumepercent to about 10 volume percent. In some aspects, the etch canutilize water, ammonium hydroxide and hydrogen peroxide, in an etch andanalogous to the so-called standard clean one (SC1). In such aspect, theratio of water to ammonium hydroxide to hydrogen peroxide can be fromabout 10:1:1 to about 100:1:1. In some aspects, the etch can use acombination of ammonium fluoride, phosphoric acid (or phosphate) andwater. Regardless of which etching chemistry is utilized, the etch canbe conducted at a temperature of from about 20° C. to about 60° C.

The prevention and/or removal of the whiskers leads to a structure ofthe type described with reference to FIGS. 16-18.

Referring next to FIGS. 21-23, a dielectric material 100 and aconductive material 103 are formed within openings 32, 34, 36, 38, 40,42, 44, 46, 48, 50, 52 and 54, as well as along outer sidewall edges 72of the container structures. Conductive material 60 of the capacitorcontainer structures can be referred to as a first capacitor electrode,and conductive material 103 can be referred to as a second capacitorelectrode. The capacitor electrodes 60 and 103, together with dielectricmaterial 100, form an array of capacitors within the array of openings32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52 and 54. The openings,together with trench 56, are shown in phantom view in FIG. 22 toindicate that such are below conductive material 103 in the shown view.

A gap 104 is illustrated beneath the portion of retaining structure 30jutting outwardly from the protective material 60 within trench 56. Itis to be understood that gap 104 can, in particular aspects, be filledthrough appropriate deposition of one or both of dielectric material 100and conductive material 102.

Transistor structures 110, 112, 114 and 116 are diagrammaticallyillustrated in FIG. 21. The transistor structures would havesource/drain regions either encompassing node locations 20, 22, 24 and26, or ohmically connected with node locations 20, 22, 24 and 26. Thetransistor devices and capacitors formed in accordance with methodologyof the present invention can be together incorporated into an array ofDRAM cells.

FIG. 23 shows regions 120 and 122 beneath the retaining structure 30filled with materials 100 and 102.

The trough in region 16 can be advantageously utilized to entirelysurround a region of a semiconductor construction. In the aspects of theinvention described above, the trough is created by forming anelectrically conductive material in trough-shaped configuration betweena memory array region and a peripheral region (see, for example, FIGS.16 and 17 where the trough is shown formed from conductive material 60over the region 16 between memory array region 14 and peripheral region18). FIGS. 24 and 25 illustrate exemplary configurations in with thetrough is formed to protect a lateral periphery of a peripheral regionfrom the isotropic etch utilized to remove material 28 from region 14(an exemplary isotropic etch is described above with reference to FIGS.16-19).

FIG. 24 shows a top view of an exemplary construction 700 comprising asubstrate having a memory array region 14 (diagrammatically illustratedas a box bounded by dashed line 708), a region 18 peripheral to thememory array where logic or other circuitry can be formed(diagrammatically illustrated as a box bounded by dashed line 704), anda region 16 between the memory array region 14 and the peripheral region18. The memory array region has a lateral periphery defined to entirelylaterally surround the memory array region, with such lateral peripherycorresponding to dashed line 708, and the peripheral region has asimilar lateral periphery defined by dashed line 704. The trough ofconductive material 60 is shown laterally surrounding an entirety of thelateral periphery of memory array region 14.

FIG. 25 shows a top view of the construction 700 illustrating that thetrough of conductive material 60 can extend entirely around the lateralperiphery of the peripheral region as well as extending entirely aroundthe lateral periphery of the memory array region.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming a semiconductor construction, comprising: formingupwardly-opening titanium-containing container structures within a firstmaterial and over a semiconductor substrate; forming silicon within theupwardly-opening container structures; after forming the silicon,removing at least some of the first material to expose outer surfaces ofthe upwardly-opening container structures; and removing the silicon withan etching solution having at least one phosphorus-and-oxygen-containingcompound therein.
 2. The method of claim 1 wherein the etching solutioncomprises one or more nitrogen-containing etching compounds.
 3. Themethod of claim 2 wherein a total concentration of the at least onephosphorus-and-oxygen-containing in the etching solution is from about0.1 volume percent to about 1 volume percent.
 4. The method of claim 2wherein a total concentration of the one or more nitrogen-containingetching compounds is from about 2 volume percent to about 50 volumepercent.
 5. The method of claim 2 wherein a total concentration of theone or more nitrogen-containing etching compounds is from about 5 volumepercent to about 25 volume percent.
 6. The method of claim 5 wherein theone more nitrogen-containing etching compounds are one or both ofammonium hydroxide and tetra-methyl ammonium hydroxide.
 7. The method ofclaim 2 wherein a total concentration of the at least onephosphorus-and-oxygen-containing compound in the etching solution isfrom about 0.2 volume percent to about 0.4 volume percent.
 8. The methodof claim 7 wherein a total concentration of the one or morenitrogen-containing etching compounds is from about 2 volume percent toabout 50 volume percent.
 9. The method of claim 7 wherein a totalconcentration of the one or more nitrogen-containing etching compoundsis from about 5 volume percent to about 25 volume percent.
 10. Themethod of claim 9 wherein the one more nitrogen-containing etchingcompounds are one or both of ammonium hydroxide and tetra-methylammonium hydroxide.
 11. The method of claim 1 wherein theupwardly-opening titanium-containing container structures comprisetitanium nitride.
 12. The method of claim 1 wherein the upwardly-openingtitanium-containing container structures comprise a layer of titanium incombination with a layer of titanium nitride.
 13. The method of claim 1wherein the first material comprises one or more of borophosphosilicateglass, spin-on-glass, silicon dioxide, phosphosilicate glass andborosilicate glass. 14-52. (canceled)
 53. A method of forming asemiconductor construction, comprising: forming upwardly-openingtitanium-containing container structures within a first material andover a semiconductor substrate; forming silicon within theupwardly-opening titanium-containing container structures; after formingthe silicon, removing at least some of the first material to exposeouter surfaces of the upwardly-opening titanium-containing containerstructures; removing the silicon with an etching solution having atleast one phosphorus-and-oxygen-containing compound therein, the etchingsolution utilized during the removal of the silicon causing formation ofwhiskers of titanium-containing material from the upwardly-openingtitanium-container structures; and exposing the titanium-containingcontainer structures and whiskers to an etch to remove the whiskers. 54.The method of claim 53 wherein the titanium-containing containerstructures include both elemental titanium and titanium nitride; andwherein the etch utilized to remove the whiskers is selective forelemental titanium relative to titanium nitride.